Title: System Verilog “<=" assignment operator has problems
Last modified: June 28, 2026

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# System Verilog “<=" assignment operator has problems

 *  [chipmunk](https://wordpress.org/support/users/chipmunklogic/)
 * (@chipmunklogic)
 * [1 week ago](https://wordpress.org/support/topic/system-verilog-assignment-operator-has-problems/)
 * Hi,
 * Looks like System Verilog Syntax highlighting has some issues on “<=” assignment
   operator.
   When I write-
 * a <=b ;
 * It is auto replaced by-
 * a ≤ b 
   These two are entirely different semantics in System Verilog.Can you fix
   this? It hurts my code snippets on my blogs.

Viewing 1 replies (of 1 total)

 *  Plugin Author [Kevin Batdorf](https://wordpress.org/support/users/kbat82/)
 * (@kbat82)
 * [1 week ago](https://wordpress.org/support/topic/system-verilog-assignment-operator-has-problems/#post-18950453)
 * Hey, this is the the font ligatures. How many code blocks do you have already?
   If you only have a few you can edit them on the settings for each code snippet.
   Pick a font without ligatures.

Viewing 1 replies (of 1 total)

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 * 1 reply
 * 2 participants
 * Last reply from: [Kevin Batdorf](https://wordpress.org/support/users/kbat82/)
 * Last activity: [1 week ago](https://wordpress.org/support/topic/system-verilog-assignment-operator-has-problems/#post-18950453)
 * Status: not resolved